光通信研究Issue(3)：71-77,7.DOI:10.13756/j.gtxyj.2026.240186
50 Gbit/s PON场景下高速LDPC编码器设计
High-Speed LDPC Encoder Design for 50 Gbit/s PON Scenario
孙邦 1李祥辉 2张艳 2肖进胜3
作者信息
- 1. 武汉大学 电子信息学院,武汉 430074||烽火通信科技股份有限公司,武汉 430205
- 2. 烽火通信科技股份有限公司,武汉 430205
- 3. 武汉大学 电子信息学院,武汉 430074
- 折叠
摘要
Abstract
[Objective]Low Density Parity Check(LDPC)codes have replaced Reed-Solomon(RS)codes as the Forward Error Correction(FEC)standard in 50 Gbit/s Passive Optical Network(PON)scenarios due to their near-Shannon-limit performance.However,their complex encoding and decoding matrices complicate the hardware implementation.[Methods]This paper im-proves the R.Urbanke(RU)encoding algorithm to support column swapping in the decoding matrix.We then design a three-stage pipelined high-speed encoder that reduces resource usage and latency,supports arbitrary code types,and robustly handles exceptions like loss indicators.[Results]Universal Verification Methodology(UVM)-based verification achieved 98%code cov-erage,confirming the encoder's ability to process the three protocol-specified code types and manage various exceptions.Field-Programmable Gate Array(FPGA)prototyping on the Intel Stratix 10 board showed that four encoders use only 14%of logical re-sources,achieving a data throughput of 50 Gbit/s.[Conclusion]This paper presents an improved RU encoding algorithm and a three-stage pipeline high-speed encoding architecture that achieves a data throughput of 50 Gbit/s with low latency and low re-source consumption in hardware implementation.The proposed solution can accurately handle all code types specified by the pro-tocol and effectively address various abnormal situations,providing an efficient and feasible approach for the hardware deployment of LDPC encoders in 50 Gbit/s PON scenarios,with significant application prospects.关键词
无源光网络/数字电路设计/低密度奇偶校验码/高速编码器Key words
PON/digital circuit design/LDPC codes/high-speed encoder分类
信息技术与安全科学引用本文复制引用
孙邦,李祥辉,张艳,肖进胜..50 Gbit/s PON场景下高速LDPC编码器设计[J].光通信研究,2026,(3):71-77,7.
