集成电路与嵌入式系统2026，Vol.26Issue(7)：17-26,10.DOI:10.20193/j.ices2097-4191.2026.0022
基于开源工具链的RISC-V处理器敏捷验证方法
Agile verification method for RISC-V processors based on open-source toolchain
摘要
Abstract
The reliance on commercial EDA tools and the complexity of environment construction in traditional processor verification workflows often hinder agile development.To overcome these bottlenecks,this paper presents an agile,core-level verification methodol-ogy for RISC-V processors driven entirely by an open-source toolchain.By leveraging Verilator as the simulation engine and the Python-based Cocotb framework's coroutine mechanism,the proposed approach achieves both high-level abstraction of test stimuli and precise cycle-level driving.Furthermore,a lightweight test architecture is designed to accelerate the feedback loop.Case studies on the open-source RISC-V Ibex core demonstrate that,compared to the traditional Universal Verification Methodology(UVM),this scheme re-duces code size by approximately 85%and compresses the iteration cycle of a single test case from hours to minutes-all while ensuring the effective verification of critical paths such as instruction execution and exception response.This solution significantly enhances early-stage design efficiency and offers a cost-effective alternative for educational experiments and prototype development.关键词
处理器验证/RISC-V/敏捷验证/开源工具链/Cocotb/VerilatorKey words
processor verification/RISC-V/agile verification/open-source toolchain/Cocotb/Verilator分类
信息技术与安全科学引用本文复制引用
胡学莹,江维..基于开源工具链的RISC-V处理器敏捷验证方法[J].集成电路与嵌入式系统,2026,26(7):17-26,10.基金项目
国家自然科学基金(62572103) （62572103）
