摘要
Abstract
FPGAs are extensively employed as interface boards in embedded systems.The software operating on these chips primarily interacts with peripheral devices.A significant challenge in verifying such FPGA software lies in developing configurable simulation models,supporting both normal and abnormal operations,based on peripheral chip specifications.Currently,these simulation models are predominantly implemented as static constructs using System Verilog/Verilog-HDL/VHDL language features.These simulation models,akin to RTL models,exhibit a structured nature.This implies that their configuration is static without supporting dynamic instantiation or teardown during the simulation.Therefore,this type of simulation model is suitable for verification scenarios in which the chip's operating mode remains unchanged during runtime.For verification scenarios where the operating mode needs to switch during runtime,using a static simulation model to simulate such scenarios requires the development of a communication interface with the veri-fication platform.Furthermore,since UVM verification platforms cannot dynamically instantiate such static simulation models,embed-ding them into a UVM environment prevents utilizing UVM's powerful class library ecosystem.To address the issues mentioned above,this paper employs the UVM standard class library,which leverages the object-oriented features of System Verilog,to construct a simu-lation model of peripheral chips.This simulation model is then embedded into the UVM verification platform.Experimental results demonstrate that the verification platform can dynamically configure the operating modes of the simulation model during runtime.In other words,the model is capable of simulating scenarios that involve switching between multiple operating modes of peripheral chips,thereby enriching the verification scenarios for FPGA software.The chip simulation model proposed in this paper,based on the UVM standard class library and integrated with the UVM verification platform,reduces to some extent the simulation complexity of peripheral chip multi-mode switching scenarios and alleviates the development and maintenance difficulties associated with simulation models for pe-ripherals featuring multiple operating modes.This approach provides a new and feasible solution for developing simulation models in the verification of FPGA software related to interface timing control.关键词
FPGA/UVM/仿真模型/验证/外围芯片Key words
FPGA/UVM/simulation model/verification/peripheral chip分类
信息技术与安全科学
