集成电路与嵌入式系统2026，Vol.26Issue(9)：15-25,11.DOI:10.20193/j.ices2097-4191.2026.0010
高精度2T0C阵列寄生电容提取与存算应用分析
Toward high-accuracy compute-in-memory:parasitic capacitance extraction and modeling for 2T0C arrays
摘要
Abstract
In compute-in-memory(CIM)employing high-density 2 T0C arrays,parasitic capacitances critically determine charge redistri-bution and bit line integration dynamics,directly impacting storage-node(SN)disturbance and computational linearity.However,the escalating computational cost of conventional extraction methods with array size obstructs efficient array-level modeling and system anal-ysis.To address this,we propose a high-accuracy approximation method for extracting parasitics from the central cell of large-scale ar-rays by leveraging the attenuating coupling of long interconnects.The method constructs a nine-port aggregated equivalent network by bundling non-adjacent word/bit lines and derives a quantitative expression for the minimum truncation distance of key capacitances under a 1%relative-error bound,enabling rapid array-level(AM)parameter extraction.This facilitates high-accuracy models for the SN and bit line capacitances(CSN and CRBL)across operational phases,accurately capturing the near-linear scaling of CRBL with array size.Simu-lations under 10×geometric scaling show a 15%accuracy improvement over the device-level model(DM).Crucially,linearity analysis based on this precise model reveals that using the low-accuracy DM would overestimate the peak integral non-linearity(INL)by approxi-mately 1.5 least significant bit(LSB).关键词
2T0C阵列/寄生电容提取/PEEC/存内计算/集成电路Key words
2T0C array/parasitic capacitance extraction/PEEC/compute-in-memory(CIM)/integrated circuit分类
信息技术与安全科学引用本文复制引用
罗振鑫,王少昊..高精度2T0C阵列寄生电容提取与存算应用分析[J].集成电路与嵌入式系统,2026,26(9):15-25,11.基金项目
国家自然科学基金项目(62474044) （62474044）
