集成电路与嵌入式系统2026，Vol.26Issue(9)：26-36,11.DOI:10.20193/j.ices2097-4191.2026.0028
应用于边缘视觉BNN推理的存算一体电路设计
Computing-in-memory circuit design for BNN inference in edge vision
摘要
Abstract
With the rapid development of edge Artificial Intelligence(AI)technologies,resource-constrained terminals impose increasingly stringent requirements on the energy efficiency of neural network inference.However,existing multi-bit neural network models and their hardware implementations generally suffer from high power consumption and complex architectures,which limit their applicability in low-power scenarios.Therefore,this work focuses on the demand for lightweight inference in edge vision tasks and proposes a low-power computing-in-memory(CIM)circuit design for convolutional inference based on Binarized Neural Networks(BNNs).Based on the charge-domain coupling principle,a compact 10T1 C SRAM CIM cell is designed.To accommodate the analog output characteristics,a low-offset comparator and an efficient input driver circuit are further developed.In the proposed architecture,three convolutional lay-ers(Conv2～Conv4)of a five-layer BNN are mapped onto the CIM array to accelerate convolution operations in BNN inference.Mean-while,to avoid frequent off-chip memory accesses during multi-layer convolution processing,a sliding-window-driven data scheduling mechanism is adopted to complete the inference process.Implemented in a 180 nm TSMC process,the architecture achieves an average power consumption of 38.67 μW and an average energy efficiency of 243 TOPS/W,demonstrating strong potential for microwatt-level edge vision inference applications.关键词
存算一体/电荷域计算/二值化神经网络/边缘视觉感知Key words
computing-in-memory/charge-domain computing/binarized neural networks/edge vision sensing分类
信息技术与安全科学引用本文复制引用
徐祥,魏淑华,陈亮,魏琦,乔飞..应用于边缘视觉BNN推理的存算一体电路设计[J].集成电路与嵌入式系统,2026,26(9):26-36,11.基金项目
北京市自然科学基金资助(L253009) （L253009）
国家自然科学基金项目(No.62334006,U25A20489) （No.62334006,U25A20489）
时空信息精密感知技术全国重点实验室开放基金(STSL2025-B-02-01(M))资助项目 （STSL2025-B-02-01(M）
