集成电路与嵌入式系统2026，Vol.26Issue(9)：83-92,10.DOI:10.20193/j.ices2097-4191.2026.0026
基于FPGA的SSI绝对值编码器缺陷检测装置设计
Design of an FPGA-based SSI absolute encoder fault detection device
摘要
Abstract
To address the low efficiency and high false positive rates of traditional SSI absolute encoder testing,this paper presents an FPGA-based automated defect detection system.The system adopts a dual-processor architecture,integrating an FPGA and an STM32 microcontroller.The FPGA performs SSI communication parsing,data acquisition,and real-time detection of anomalies such as skip-ping,looping,and dead codes,while the STM32 handles stepper motor control and user interaction.By integrating the incremental dy-namic-threshold algorithm with high-speed buffering logic,the proposed system enables real-time analysis and accurate anomaly detec-tion of encoder outputs.Experimental results demonstrate that the proposed system achieves high detection and recognition accuracy and is capable of effectively resisting interference in complex environments.The proposed system offers a cost-effective,high-performance solution for efficient and reliable encoder inspection and quality control in industrial applications.关键词
SSI绝对值编码器/FPGA/STM32/双处理器架构/编码增量动态阈值/实时缺陷检测Key words
SSI absolute encoder/FPGA/STM32/dual-processor architecture/coded incremental dynamic threshold/real-time defect detection分类
信息技术与安全科学引用本文复制引用
徐晨晨,赵忠鑫,王安红..基于FPGA的SSI绝对值编码器缺陷检测装置设计[J].集成电路与嵌入式系统,2026,26(9):83-92,10.基金项目
临职项目(2024YJKT-006) （2024YJKT-006）
