测试科学与仪器2026，Vol.17Issue(3)：435-445,11.DOI:10.62756/jmsi.1674-8042.2026037
低功耗HMAC硬件架构的设计与分析
Design and analysis of a low-power HMAC hardware architecture
李锦明 1晁志恒 1韩昕烨2
作者信息
- 1. 中北大学 半导体与物理学院,山西 太原 030051
- 2. 利物浦大学 电子电气工程系,布朗洛山 L69 7ZX
- 折叠
摘要
Abstract
Hash-based message authentication code(HMAC)modules often operate for extended periods in power-constrained embedded security terminals and edge-trusted computing devices,easily creating a significant energy bottleneck issues.To address this challenge,we propose a module-level collaborative low-power hardware architecture for HMAC-SHA-256.Exploiting the phased computational characteristics of the HMAC algorithm,a top-level finite state machine(FSM)coordinates clock gating,datapath gating,and power gating to selectively disable inactive modules across different computation stages,thereby reducing clock activity,redundant switching in combinational logic,and leakage power.Gate-level simulations based on an SMIC 55 nm technology at 100 MHz demonstrate that,without degrading operating frequency,the proposed architecture reduces total power consumption from 40.830 mW to 19.902 mW(a 51.3%reduction),while achieving an approximately 14.8%reduction in logic-synthesis-equivalent area.These results indicate that the proposed approach effectively minimizes task energy under strict performance constraints and provides a reusable low-power design methodology for HMAC hardware implementations in resource-constrained environments.关键词
HMAC-SHA256/低功耗硬件/时钟门控/电源门控/数据通路门控/嵌入式安全系统Key words
HMAC-SHA256/low-power hardware/clock gating/power gating/datapath gating/embedded security system引用本文复制引用
李锦明,晁志恒,韩昕烨..低功耗HMAC硬件架构的设计与分析[J].测试科学与仪器,2026,17(3):435-445,11.
