测试科学与仪器2026，Vol.17Issue(3)：446-458,13.DOI:10.62756/jmsi.1674-8042.2026038
一种面向存算一体的具有片上自校准的三级流水线读出电路
A three-stage pipeline readout circuit with on-chip self-calibration for computing-in-memory
摘要
Abstract
This paper presents a high-precision three-stage pipeline readout circuit for computing-in-memory(CIM)architectures with on-chip self-calibration.The proposed readout circuit addresses the challenges of precision errors in analog computing and enhances computing throughput.A current subtraction error calibration is proposed to effectively compensate for current mirror mismatches,ensuring accurate bypass current by employing negative feedback and capacitor storage.In addition,a resistance variation calibration is proposed to suppress the non-linearity of current-to-voltage conversion circuits with ADC-assisted offset detection.Furthermore,a three-stage pipeline scheme is proposed to enhance computing throughput by parallel processing.Simulated in a 55 nm process,the proposed current subtraction error calibration improves the precision of adjacent column current subtraction by 58.3%compared to the case without calibration.Moreover,the computing throughput of the proposed readout circuit reaches 1 908 giga operations per second(GOPS).Under 8-bit weight input and 8-bit output quantization,the proposed readout circuit demonstrates significant improvements in inference accuracy on MNIST,CIFAR-10,and ImageNet datasets by 7.6%,6.6%,and 8.9%,respectively.关键词
存内计算/读出电路/片上自校准/流水线架构/电流失配校准Key words
computing-in-memory(CIM)/readout circuit/on-chip self-calibration/pipeline architecture/current error calibration引用本文复制引用
陈建涛,乔洋,虞致国,顾晓峰..一种面向存算一体的具有片上自校准的三级流水线读出电路[J].测试科学与仪器,2026,17(3):446-458,13.基金项目
This work was supported by Key Research Project of Jiangsu Province(No.BE2023019-3). （No.BE2023019-3）
