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三维集成封装中的TSV互连工艺研究进展

吴向东

电子与封装Issue(9):1-5,13,6.
电子与封装Issue(9):1-5,13,6.

三维集成封装中的TSV互连工艺研究进展

Research Status of Through-Silicon Via Interconnection for 3D Integration Technology

吴向东1

作者信息

  • 1. 中国电子科技集团公司第43研究所,合肥 230088
  • 折叠

摘要

Abstract

  To meet the growing trend of Moore’s Law, chip technology has come“More than Moore”era of 3D integration. Further miniaturization of electronic systems and performance, 3D integration solution is needed more and more. As for the demand-driven, the through-silicon vias(TSV)interconnect technology emerged as the three-dimensional integration and it is one of key techniques for 3D integration and wafer-level packaging. TSV integration is compared with raditional assembly methods, there are several advantages to adopt this technology. The main ones are: reduction of interconnects length, electrical performance improvement induced and wider range of possibilities for heterogeneous integration. 3D integration would then allow to build systems including several families of components usually hardly compatible, like RF devices, memory, logic and MEMS. In this paper, nearly two years of foreign literature about 3D-TSV integrated interconnect technology and processes are summarized, the future trend of technology is discussed.

关键词

互连/三维集成/硅通孔

Key words

interconnection/3D integration/TSV

分类

信息技术与安全科学

引用本文复制引用

吴向东..三维集成封装中的TSV互连工艺研究进展[J].电子与封装,2012,(9):1-5,13,6.

电子与封装

1681-1070

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