电子与封装Issue(5)：23-27,32,6.
用于锁相环快速锁定的鉴频鉴相器设计
A Fast Acquisition Phase Frequency Detector for Phase Locked Loops
寇先果 1高博 1龚敏1
作者信息
- 1. 四川大学物理科学与技术学院微电子学系，成都610064
- 折叠
摘要
Abstract
Because of the effect on the lock speed of phase locked loop by the blind zone of phase frequency detector(PFD), the paper proposes a PFD circuit structure which can realise a quick lock acquisition of a phase locked loop. Based on the traditional PFD, the structure is designed with internal signal to control circuit logic, and its transfer characteristic is nonlinear. When the input phase error is lager thanπ, the reset pulse signal is suppressed, and the input clock edge is avoided missing. The blind zone is eliminated effectively to speed up the lock acquisition of a phase locked loop. Based on SMIC 0.18μm standard CMOS process, the PFD circuit structure is designed, simulated, analysed and veriifed in full custom design method. The simulation results indicate that the PLL with the proposed PFD circuit structure can accelerate lock acquisition by 34.27%, and its locking time is 2.95 μs working in the frequency of 400 MHz.关键词
鉴频鉴相器/锁相环/盲区/锁定时间Key words
PFD/PLL/blind zone/acquisition time分类
信息技术与安全科学引用本文复制引用
寇先果,高博,龚敏..用于锁相环快速锁定的鉴频鉴相器设计[J].电子与封装,2014,(5):23-27,32,6.
