电子与封装Issue(4)：31-35,40,6.
一款DSP指令集模拟器性能优化技术研究
Research on Optimization Techniques of Instruction Set Simulator for ZW100 DSP
阮园 1王胜 1张庆文1
作者信息
- 1. 中国电子科技集团公司第58研究所，江苏无锡214035
- 折叠
摘要
Abstract
This paper concentrates on the instruction-accurate Instruction Set Simulator (ISS) which simulates the CPU and main memory of the ZW100 DSP chip. In the modern embedded system design process, ISS can help to validate the processor which does not yet exist, as well as the compiler design, the operating system design, the performance test etc. At present, the research of the ISS is concentrated on improving the simulator speed on the condition of its flexibility. This paper aims to optimize the simulate speed. Based on the general optimization techniques, improves the performance of ISS by the optimization of simulate strategy, memory management and decode algorithm. It has been tested that the optimization strategies of this paper can improve the performance of ISS.关键词
指令集模拟器/优化技术/虚拟页表/预执行缓存Key words
instruction set simulator/optimization strategy/virtual page/pre-execute cache分类
信息技术与安全科学引用本文复制引用
阮园,王胜,张庆文..一款DSP指令集模拟器性能优化技术研究[J].电子与封装,2013,(4):31-35,40,6.
