电子与封装Issue(9)：29-32,4.
一种应用于流水线ADC的采样保持电路设计
A Sample/Hold Circuit for Pipelined ADCs
朱晓宇 1居水荣 2石乔林 1李华3
作者信息
- 1. 江南大学物联网工程学院，江苏无锡214122
- 2. 中国电子科技集团公司第58研究所，江苏无锡 214035
- 3. 中国电子科技集团公司第58研究所，江苏无锡 214035
- 折叠
摘要
Abstract
A sample and hold circuit for 8 bit 100 MSPS pipelined ADCs is presented. A two stage ampliifer with cascade miller compensation for the capacitor lfip around architecture and bottom plane sampling technique is used. The traditional bootstrapped switch is improved to reduce the area without impacting performance. The circuit is based on CSMC 0.18 μm CMOS process and simulated by Spectre. Dynamic parameters are analyzed with Matlab, which shows the SFDR is 74.7 dB and SINAD is 60.8 dB.关键词
采样保持/栅压自举/流水线ADCKey words
sample and hold/bootstrapped switch/pipelined ADCs分类
信息技术与安全科学引用本文复制引用
朱晓宇,居水荣,石乔林,李华..一种应用于流水线ADC的采样保持电路设计[J].电子与封装,2015,(9):29-32,4.
