电子元件与材料2017，Vol.36Issue(11)：52-59,8.DOI:10.14106/j.cnki.1001-2028.2017.11.010
一种用于Σ-ΔADC的低功耗数字抽取滤波器
A low power digital decimation filter for Sigma-delta ADC
摘要
Abstract
A low-power digital decimation filter for Sigma-Delta ADC was designed. The filter consisted of a CIC filter, a compensation filter and a half-band filter. In the design, the power consumption of the whole filter was reduced by using Noble's identity principle, polyphase decomposition technique and CSD encoding technique. According to the parity of the length and the symmetry of the coefficients of the compensation filter and the half-band filter, a parity optimization method was presented to optimize the structure of the filter again. This method could also further reduce the power consumption of the entire filter, therefore, the purpose of low power consumption was achieved. Based on the 110 nm CMOS process, and under the circumstance of 10 MHz sampling frequency, 5 kHz sinusoidal input signal frequency and 256 times down sampling rate, the post simulation results show that the signal-to-noise and distortion ratio(SNDR) of the filter is 91.5 dB, the spurious free dynamic range(SFDR) is 97.0 dB, and the effective number of bits(ENOB) is 14.91 bit. The area of digital circuit (with SPI) is about 0.31 mm×0.81 mm, and the total power consumption is only 376μW at a power supply of 1.5 V.关键词
Σ-ΔADC/低功耗/数字抽取滤波器/多相分解/系数对称/奇偶优化法Key words
Sigma-Delta ADC/low power/digital decimation filter/polyphase decomposition/coefficient symmetry/parity optimization method分类
信息技术与安全科学引用本文复制引用
汪杰,刘慧君,谢亮,金湘亮..一种用于Σ-ΔADC的低功耗数字抽取滤波器[J].电子元件与材料,2017,36(11):52-59,8.基金项目
国家自然科学基金资助(No.61274043) （No.61274043）
国家自然科学基金资助((No.62173010) （(No.62173010）
湖南省自然科学杰出青年基金资助((No.2015JJ1014) （(No.2015JJ1014）
