首页|期刊导航|半导体学报（英文版）|Towards efficient deep neural network training by FPGA-based batch-level parallelism
Towards efficient deep neural network training by FPGA-based batch-level parallelismOACSCDCSTPCD
Towards efficient deep neural network training by FPGA-based batch-level parallelism
Cheng Luo;Man-Kit Sit;Hongxiang Fan;Shuanglong Liu;Wayne Luk;Ce Guo
State Key Laboratory of ASIC and System, Fudan University, Shanghai 200050, ChinaDepartment of Computing, Imperial College London, London, United KingdomDepartment of Computing, Imperial College London, London, United KingdomDepartment of Computing, Imperial College London, London, United KingdomDepartment of Computing, Imperial College London, London, United KingdomDepartment of Computing, Imperial College London, London, United Kingdom
deep neural networktrainingFPGAbatch-level parallelism
deep neural networktrainingFPGAbatch-level parallelism
《半导体学报（英文版）》 2020 (2)
55-66,12
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