考虑模块翻转和空白区域再分配的基于静电场的固定边框布图规划OACSTPCD

Currently,analytical methods have achieved the best results for VLSI floorplanning.Module flipping has real applications and can further optimize floorplanning results,but analytical methods cannot handle modules flipping in floorplaning.Therefore,this paper attempts to solve this problem by using a unified analytical method,and proposes a new force,i.e.,the flipping force,for modules flip-ping.The flipping force can guide each module's flipping to its desired direction based on wire length optimization during the global floor-planning stage.In addition,based on the electrostatic field model,this paper designs a new global floorplanning flow in which special treatment is applied to the density calculation of large-size modules.The aim is to reduce the repulsion of these modules and allow other modules to be placed closer to them,thus achieving a more uniform distribution of modules.To better utilize the whitespace between the floorplan boundary and large modules,a gap handling method is proposed.Finally,a post-floorplanning stage is applied to further opti-mize the floorplanning result.This stage involves re-optimizing the modules flipping directions using a mixed-integer linear program-ming,followed by applying our proposed new whitespace redistribution method.The whitespace redistribution method reduces the number of constraints in the linear programming problem and allows multiple rounds of optimization,leading to a more effective reduction of wire length compared to previous methods.The experimental results on HB±and ami49_x benchmark circuits show that the proposed floor-planning algorithm achieves an average half-perimeter wire length reduction of at least 13.3％and 13.7％,respectively,compared to state-of-the-art floorplanning algorithms.