一种16位110 dB无杂散动态范围的低功耗SAR ADCOA北大核心CSTPCD
A 16-Bit Low Power SAR ADC with 110 dB Spurious Free Dynamic Range
该文设计了一款 16位、转换速率为 625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC).改进的采样保持电路结构,优化了采样线性度和噪声性能.采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗.利用扰动注入技术提升ADC的线性度.比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度.芯片采用CMOS 0.18µm工艺设计和流片,ADC核心面积为 1.15 mm2.测试结果表明,在 1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达 8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW.
A 16-bit 625 kS/s Successive Approximation Register Analog-to-Digital Converter(SAR ADC)is presented.An improved sampling and hold circuit is proposed to optimize sampling linearity and noise performance.Segmented Capacitor Digital-to-Analog Converter(CDAC)is designed and hybrid capacitor switching method is adopted to reduce layout area and switching energy.Dither injection technique is used to improve ADC's linearity.Two-stage integrating preamplifier is adopted to reduce comparator's noise.Output offset storage and optimized circuit design techniques reduce comparator's offset and noise induced by offset calibration.Comparator speed is also improved by circuit design.The prototype is fabricated using CMOS 0.18µm process and occupies an active area of 1.15 mm2.With 1 kHz sinusoid input,the measured differential input peak-to-peak amplitude is 8.8 V.Signal to Noise and Distortion(SINAD)and Spurious Free Dynamic Range(SFDR)are 85.9 dB and 110 dB respectively.Differential Nonlinearity(DNL)and Integral Nonlinearity(INL)are-0.27/+0.32 LSB and-0.58/+0.53 LSB respectively with a power consumption of 4.31 mW.
邢向龙;王倩;康成;彭姜灵;李清;俞军
复旦大学微电子学院,上海 200433上海复旦微电子集团股份有限公司,上海 200438
电子信息工程
模数转换器数模转换器低噪声比较器失调校准采样保持逐次逼近寄存器
analog-to-digital converter(ADC)digital-to-analog converter(DAC)low noise comparatoroffset calibrationsample and holdsuccessive approximation register(SAR)
《电子科技大学学报》 2024 (002)
185-193 / 9
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