一款0.16mm2基于180nm CMOS采用全局去偏斜的半速率8×2.5 Gb/s时钟转发架构接收机OACSTPCD
A 0.16 mm2 8×2.5 Gb/s clock-forwarding half-rate receiver with global de-skew in 180 nm CMOS
在时钟转发架构的高速有线通信接收机中,需要去偏斜电路实现时钟与数据之间的最佳采样关系,并保证多路数据的同步.本文提出了 一种全局去偏斜方案,仅采用一路数据与时钟进行对齐,并通过时钟延时匹配与分布技术实现多路数据同步,减小了各通道独立去偏斜方案带来的功耗与面积开销.所提出的接收机由8路数据通道、1路半速率转发时钟通道与基于延迟锁定环路的全局去偏斜电路构成.基于180 nm CMOS工艺,在2.5 Gb/s数据率下,可去除输入时钟与数据任意偏斜,得到位于数据中心的采样相位,同时具有时钟占空比校准能力.在1.8 V电源电压下,所提出的接收机总功耗为187 mW,总面积为0.16 mm2,对比各通道独立去偏斜方案,功耗和面积开销分别节约了 45.2％与62.8％.
In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is pro-posed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm2,saving 45.2％and 62.8％of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.
杨力宏;李世新;韩晨曦;云越恒;刘术彬;赵潇腾;朱樟明
西安电子科技大学,西安 710071
电子信息工程
时钟转发多路接收机全局去偏斜延迟锁定环路时钟分布数据同步半速率
clock forwardingmulti-channel receiversglobal de-skewdelay-locked loopsclock distributiondata synchronizationhalf rate
《集成电路与嵌入式系统》 2024 (004)
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高速射频模数转换器芯片研究(2022YFB4401900);高能效多电平宽范围高速数据接口接收机关键技术研究(62374126);高效模拟前端集成电路和集成系统(62021004);超高速模数转换器集成电路测试验证系统(62227816).
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