集成电路与嵌入式系统2024，Vol.24Issue(4)：1-9,9.
一款0.16mm2基于180nm CMOS采用全局去偏斜的半速率8×2.5 Gb/s时钟转发架构接收机
A 0.16 mm2 8×2.5 Gb/s clock-forwarding half-rate receiver with global de-skew in 180 nm CMOS
摘要
Abstract
In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is pro-posed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm2,saving 45.2％and 62.8％of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.关键词
时钟转发/多路接收机/全局去偏斜/延迟锁定环路/时钟分布/数据同步/半速率Key words
clock forwarding/multi-channel receivers/global de-skew/delay-locked loops/clock distribution/data synchronization/half rate分类
信息技术与安全科学引用本文复制引用
杨力宏,李世新,韩晨曦,云越恒,刘术彬,赵潇腾,朱樟明..一款0.16mm2基于180nm CMOS采用全局去偏斜的半速率8×2.5 Gb/s时钟转发架构接收机[J].集成电路与嵌入式系统,2024,24(4):1-9,9.基金项目
高速射频模数转换器芯片研究(2022YFB4401900) （2022YFB4401900）
高能效多电平宽范围高速数据接口接收机关键技术研究(62374126) （62374126）
高效模拟前端集成电路和集成系统(62021004) （62021004）
超高速模数转换器集成电路测试验证系统(62227816). （62227816）
