基于全数字锁相环优化的快速跳频技术研究OACSTPCD

Aiming at the shortcomings of all digital phase-locked loop(ADPLL)in terms of frequency hopping time,signal quality,fre-quency stepping,the loop structure and digital phase-locked algorithm of ADPLL are optimized,and a new type of all digital phase-locked loop structure is designed.This structure adopts a Fast Frequency to Voltage Converter(FVC)to replace the digital frequency and phase discriminator and digital filter in ADPLL.FVC calculates the output frequency value directly by doubling the reference frequency and counting the feedback frequency,thereby determining the error between the output frequency and the target output frequency.By estab-lishing a functional relationship between frequency error and voltage adjustment,FVC controls the fast locking of the output frequency,achieving small frequency steps and high-quality fast synthesis frequency output.Finally,the feasibility of the new all digital phase-locked loop structure has been verified through simulation and actual measurement.The actual test results show that the frequency near end spurious synthesized by this technology is-87 dBc,the minimum frequency step can reach 191 Hz,and the minimum frequency hopping time is 3.9 μs.