集成电路与嵌入式系统2024，Vol.24Issue(4)：10-16,7.
基于全数字锁相环优化的快速跳频技术研究
Research on fast frequency hopping technology based on all digital phase locked loop optimization
王锋 1郭中会 1徐国栋 1庞洋 1张一萌1
作者信息
- 1. 天津七一二通信广播股份有限公司,天津 300462
- 折叠
摘要
Abstract
Aiming at the shortcomings of all digital phase-locked loop(ADPLL)in terms of frequency hopping time,signal quality,fre-quency stepping,the loop structure and digital phase-locked algorithm of ADPLL are optimized,and a new type of all digital phase-locked loop structure is designed.This structure adopts a Fast Frequency to Voltage Converter(FVC)to replace the digital frequency and phase discriminator and digital filter in ADPLL.FVC calculates the output frequency value directly by doubling the reference frequency and counting the feedback frequency,thereby determining the error between the output frequency and the target output frequency.By estab-lishing a functional relationship between frequency error and voltage adjustment,FVC controls the fast locking of the output frequency,achieving small frequency steps and high-quality fast synthesis frequency output.Finally,the feasibility of the new all digital phase-locked loop structure has been verified through simulation and actual measurement.The actual test results show that the frequency near end spurious synthesized by this technology is-87 dBc,the minimum frequency step can reach 191 Hz,and the minimum frequency hopping time is 3.9 μs.关键词
频率合成技术/快速跳频/快速频率-电压转换器/全数字锁相环Key words
frequency synthesis technology/fast frequency hopping/FVC/ADPLL分类
信息技术与安全科学引用本文复制引用
王锋,郭中会,徐国栋,庞洋,张一萌..基于全数字锁相环优化的快速跳频技术研究[J].集成电路与嵌入式系统,2024,24(4):10-16,7.
