计算机工程与科学2024，Vol.46Issue(4)：606-614,9.DOI:10.3969/j.issn.1007-130X.2024.04.005
可变流水级SM4加解密算法硬件设计及FPGA实现
Hardware design and FPGA implementation of a variable pipeline stage SM4 encryption and decryption algorithm
朱麒瑾 1陈小文 2鲁建壮2
作者信息
- 1. 国防科技大学计算机学院,湖南 长沙 410073||先进微处理器芯片与系统重点实验室,湖南 长沙 410073||电子科技大学集成电路科学与工程学院,四川 成都 610054
- 2. 国防科技大学计算机学院,湖南 长沙 410073||先进微处理器芯片与系统重点实验室,湖南 长沙 410073
- 折叠
摘要
Abstract
As the first commercial cryptographic algorithm in China,SM4 algorithm is widely used in data encryption storage and information encryption communication and other fields due to its advantages of simple and easy implementation of algorithm structure,fast encryption and decryption speed and high security.With the variable pipeline stage SM4 encryption and decryption algorithm hardware design and FPGA implementation as the research topic,this study focuses on the performance differences in designs with different pipeline stages.A controllable pipeline stage SM4 encryption and decryption circuit is de-signed and encapsulated into an IP core with AXI and APB interfaces.Based on XILINX ZYNQ devices,a small SoC is constructed on the XILINX ZYNQ-7020 development board,and the designed SM4 IP core is mounted onto the AXI bus for simulating real-world scenarios and conducting performance tests.The correctness of the design functionality is verified by comparing software encryption and decryption data with simulated data.Testing the performance of different pipeline stages helps identify the most suitable pipeline stage number.关键词
SM4/流水线设计/ZYNQ/AXI/APBKey words
SM4/pipeline design/ZYNQ/AXI/APB分类
信息技术与安全科学引用本文复制引用
朱麒瑾,陈小文,鲁建壮..可变流水级SM4加解密算法硬件设计及FPGA实现[J].计算机工程与科学,2024,46(4):606-614,9.
