基于Veloce仿真器的DDR3 SDRAM故障模拟IP核设计OACSTPCD
Design of DDR3 SDRAM Fault Simulation IP Core Based on Veloce Emulator
DDR3 SDRAM在高安全领域仍有广泛应用,为了在系统设计早期评估存储器故障对系统的影响,基于Veloce硬件仿真器设计了故障模拟IP核.该IP核基于Tcl脚本和BackDoor技术开发故障生成模块,能够模拟存储器器件软错误和硬错误故障;利用Tk工具箱整合了操作流程,提供了GUI操作界面,可设置故障发生的时机和故障点位.实验表明,该设计可以在仿真器中实现对该类存储器的故障模拟.
DDR3 SDRAM is widely used in high security fields.In order to evaluate the impact of its fault on the system,a fault simulation IP core is designed based on the Veloce hardware emulator to evaluate the fault response of the memory in the early stage of system design.A fault generation module based on Tcl script and BackDoor technology is developed,which can simulate the soft and hard faults of memo-ry devices.Tk toolbox is used to integrate the operation process and provide a GUI operation interface,which can set the timing and fault point of the fault.Experiment shows that the design can simulate soft and hard errors of this kind of memory in the Veloce emulator.
田毅;刘畅;谢莉;马世耀
中国民航大学安全科学与工程学院,天津 300300四川九洲空管科技有限责任公司,四川 绵阳 621000
电子信息工程
硬件仿真故障模拟DDR3 SDRAMIP核
hardware emulationfault simulationDDR3 SDRAMIP core
《电子器件》 2024 (002)
338-343 / 6
中央高校基本科研业务费项目-自然科学类一般项目(3122019165)
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