电子器件2024，Vol.47Issue(2)：338-343,6.DOI:10.3969/j.issn.1005-9490.2024.02.007
基于Veloce仿真器的DDR3 SDRAM故障模拟IP核设计
Design of DDR3 SDRAM Fault Simulation IP Core Based on Veloce Emulator
摘要
Abstract
DDR3 SDRAM is widely used in high security fields.In order to evaluate the impact of its fault on the system,a fault simulation IP core is designed based on the Veloce hardware emulator to evaluate the fault response of the memory in the early stage of system design.A fault generation module based on Tcl script and BackDoor technology is developed,which can simulate the soft and hard faults of memo-ry devices.Tk toolbox is used to integrate the operation process and provide a GUI operation interface,which can set the timing and fault point of the fault.Experiment shows that the design can simulate soft and hard errors of this kind of memory in the Veloce emulator.关键词
硬件仿真/故障模拟/DDR3 SDRAM/IP核Key words
hardware emulation/fault simulation/DDR3 SDRAM/IP core分类
电子信息工程引用本文复制引用
田毅,刘畅,谢莉,马世耀..基于Veloce仿真器的DDR3 SDRAM故障模拟IP核设计[J].电子器件,2024,47(2):338-343,6.基金项目
中央高校基本科研业务费项目-自然科学类一般项目(3122019165) （3122019165）
