电子与封装2024，Vol.24Issue(5)：59-64,6.DOI:10.16257/j.cnki.1681-1070.2024.0061
国产FPGA高速串行接口误码率测试软件设计
Software Design of High-Speed Serial Interface Error Ratio Test Based on Domestic FPGA
李卿 1段辉鹏 1惠锋1
作者信息
- 1. 无锡中微亿芯有限公司,江苏无锡 214072
- 折叠
摘要
Abstract
With the widespread use of the FPGA with embedded high-speed serial interface,the monitoring of signal quality becomes extremely important.A high-speed serial interface error ratio test software based on domestic FPGA chip is designed,which uses a soft core to achieve high-speed serial interface error ratio statistics and dynamical reconfiguration of attributes,and real-time monitoring is carried out by using host computer software,thus effectively improving the test efficiency.The method and steps for the software to perform error ratio test are detailed through practical example,and the validity of the software test is verified.The research results indicate that the software can provide a good user experience and high test efficiency,and plays a positive role in promoting the localization process of FPGA.关键词
FPGA/高速串行接口/误码率Key words
FPGA/high-speed serial interface/error ratio分类
信息技术与安全科学引用本文复制引用
李卿,段辉鹏,惠锋..国产FPGA高速串行接口误码率测试软件设计[J].电子与封装,2024,24(5):59-64,6.
