Machine learning algorithm partially reconfigured on FPGA for an image edge detection systemOA
Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
Gracieth Cavalcanti Batista;Johnny Öberg;Osamu Saotome;Haroldo F.de Campos Velho;Elcio Hideiti Shiguemori;Ingemar Söderquist
Division of Electronic and Embedded Systems,KTH Royal Institute of Technology,Stockholm 164 40,Sweden||Electronic Engineering Division,Aeronautics Institute of Technology,São José dos Campos SP 12228-900,BrazilDivision of Electronic and Embedded Systems,KTH Royal Institute of Technology,Stockholm 164 40,SwedenElectronic Engineering Division,Aeronautics Institute of Technology,São José dos Campos SP 12228-900,BrazilLaboratory of Applied Computing and Mathematics,National Institute for Space Research,São José dos Campos SP 12227-900,BrazilElectronic Engineering Division,Aeronautics Institute of Technology,São José dos Campos SP 12228-900,Brazil||Department of C4ISR,Institute of Advanced Studies,São José dos Campos SP 12228-001,BrazilDivision of Electronic and Embedded Systems,KTH Royal Institute of Technology,Stockholm 164 40,Sweden||Saab AB,Linköping 581 88,Sweden
Dynamic partial reconfiguration(DPR)Field programmable gate array(FPGA)implementationImage edge detectionSupport vector regression(SVR)Unmanned aerial vehicle(UAV)pose estimation
Dynamic partial reconfiguration(DPR)Field programmable gate array(FPGA)implementationImage edge detectionSupport vector regression(SVR)Unmanned aerial vehicle(UAV)pose estimation
《电子科技学刊》 2024 (2)
48-68,21
This work was financially supported by the National Council for Scientific and Technological Development(CNPq,Brazil),Swedish-Brazilian Research and Innovation Centre(CISB),and Saab AB under Grant No.CNPq:200053/2022-1the National Council for Scientific and Technological Development(CNPq,Brazil)under Grants No.CNPq:312924/2017-8 and No.CNPq:314660/2020-8.
评论