电子与封装2024，Vol.24Issue(6)：121-128,8.DOI:10.16257/j.cnki.1681-1070.2024.0143
三维异构集成的发展与挑战
Developments and Challenges of 3D Heterogeneous Integration
马力 1项敏 1吴婷1
作者信息
- 1. 通富微电子股份有限公司,江苏南通 226000
- 折叠
摘要
Abstract
3D heterogeneous integration technology is a key technology for the future semiconductor industry as it drives the change of semiconductor technology and breaks through the limitations imposed by the approaching limits of the manufacturing process with innovations in packaging technology.Key technologies in 3D heterogeneous integration technology include silicon-through-via/glass-through-via technology for signal transmission and interconnection,redistribution layer technology and micro-bump technology,which are integrated to facilitate the development of 3D heterogeneous integration technology.Efficient and reliable communication interconnection between chips is driving the development of 3D heterogeneous integration technology,and parallel interconnect interfaces are widely used at present.Interconnect interfaces for heterogeneous integration are not inherently superior or inferior,and should be judged solely on the basis of whether or not they meet the application requirements.The latest advances in 3D heterogeneous integration technology in optoelectronic integrated technology and antenna in package are described in detail.The co-design challenges faced by the development of 3D heterogeneous integration are summarized and overviewed in terms of chip packaging design and co-modeling simulation.It is proposed to combine machine learning,digital twin and other technologies with 3D heterogeneous integration packaging in the future,focusing on the development of system-level optimization as well as co-design development to achieve more efficient platform prediction.关键词
三维异构集成/微凸点/互联接口/芯片封装设计Key words
3D heterogeneous integration/micro-bump/interconnection interface/chip packaging design分类
信息技术与安全科学引用本文复制引用
马力,项敏,吴婷..三维异构集成的发展与挑战[J].电子与封装,2024,24(6):121-128,8.
