电子与封装2024，Vol.24Issue(7)：63-68,6.DOI:10.16257/j.cnki.1681-1070.2024.0080
R-DSP中二级Cache控制器的优化设计
Optimization Design of Secondary Cache Controller in R-DSP
摘要
Abstract
Aiming at the important role of the secondary cache controller(L2)for improving the access efficiency and overall performance of R-DSP,and combining the memory security maintenance and multi-request access arbitration involved in the L2,the following optimizations are implemented on the basis of the L2 in the existing R-DSP.Firstly,the multi-block storage organization structure is adopted to improve the efficiency of memory access.Secondly,the first-level cache controller requests and external memory requests are processed in parallel to reduce the request processing cycle.Finally,bandwidth management and storage protection functions are added to reasonably arbitrate memory access requests and maintain storage security.Experimental results show that compared with the traditional design,the new design realizes bandwidth management access arbitration while protecting the security of secondary storage.Compared with L2 in the existing R-DSP,the maximum number of memory access requests that can be responded to in a single beat of the new design is increased by 100％,and the average processing clock cycles of first-level requests and external memory requests are reduced by 25％and 19.6％respectively.关键词
DSP/二级Cache/存储结构/并行处理/存储保护/带宽管理Key words
DSP/secondary cache/storage structure/parallel processing/storage protection/bandwidth management分类
信息技术与安全科学引用本文复制引用
谭露露,谭勋琼,白创..R-DSP中二级Cache控制器的优化设计[J].电子与封装,2024,24(7):63-68,6.基金项目
湖南省教育厅优秀青年科研项目(22B0287) （22B0287）
