计算机工程与科学2024，Vol.46Issue(7)：1185-1192,8.DOI:10.3969/j.issn.1007-130X.2024.07.006
基于RISC-V的超标量处理器的ROB压缩方法
ROB compression method based on RISC-V superscalar processor
王洁 1付丹阳2
作者信息
- 1. 大连理工大学软件学院,辽宁 大连 116081
- 2. 大连理工大学软件学院,辽宁 大连 116081||北京开源芯片研究院,北京 100085
- 折叠
摘要
Abstract
RISC-V instruction set has the advantages of flexibility and scalability,and vector exten-sion is one of its extended instruction sets.When implementing vector extention,it is necessary to split the vector instruction into multiple microinstructions.If each microinstruction occupies a reordering buffer(ROB)entry,there will be certain information redundancy,and will reduce the number of in-structions executed in parallel(in-flight instructions)in the CPU,affecting processor performance.Based on the method of decoupling the storage of instructions and microinstructions in ROB,a new queue RAB is used to store information such as the renaming mapping relationship of the destination register of each microinstruction,and each ROB stores only the common information of the microin-structions derived from its corresponding instruction.ROB and RAB respectively control the commit and walk of instructions and microinstructions,which reduces the redundancy of stored information and alleviates the problem caused by too many microinstructions for vector instruction splitting.On the basis of the above method,this paper implements the ROB compression of scalar instructions at the same time,increasing the maximum number of in-flight instructions with the same number of ROB entries.The final simulation results show that this method effectively improves the performance of the processor.关键词
RISC-V/超标量/处理器/ROB压缩Key words
RISC-V/superscalar/processor/ROB compression分类
信息技术与安全科学引用本文复制引用
王洁,付丹阳..基于RISC-V的超标量处理器的ROB压缩方法[J].计算机工程与科学,2024,46(7):1185-1192,8.
