计算机工程与科学2024，Vol.46Issue(7)：1202-1209,8.DOI:10.3969/j.issn.1007-130X.2024.07.008
面向56 Gb/s高速SerDes接收机DSP设计
DSP design for 56 Gb/s high-speed SerDes receiver
摘要
Abstract
The high-speed serial interface chip is an important IP in high-performance interconnect network communication.This paper proposes a DSP design for 56 Gb/s high-speed Serdes receivers,in response to the problem of high bit error rate caused by severe channel attenuation over long transmis-sion distances in high-performance interconnect network backplane communication using 56 Gb/s four pulse amplitude modulation(PAM4)signals.The DSP adopts a 64-channel parallel structure and processes the digitized signal from the receiver through a 16-Tap feed forward equalizer(FFE)and a de-cision feedback equalizer(DFE).By using the K-means clustering algorithm to generate dynamically changing DFE decision levels and combining it with the least mean square(LMS)algorithm,it can han-dle the equalization problem under different channel attenuation of 15～35 dB.To verify the perform-ance of the algorithm,an experimental verification platform based on analog frontend chips and field programmable gate arrays(FPGA)was constructed.The experimental results indicate that the channel attenuation is 15～35 dB@14 GHz at a speed of 56 Gb/s,the error rate is less than 5e-10.关键词
K-均值算法/前向反馈均衡/预判决反馈均衡/自适应均衡Key words
K-means algorithm/feed forward equalization/decision feedback equalization/adaptive e-qualization分类
信息技术与安全科学引用本文复制引用
胡小月,王强,吕方旭,许超龙,张锦..面向56 Gb/s高速SerDes接收机DSP设计[J].计算机工程与科学,2024,46(7):1202-1209,8.基金项目
国家重点研发计划(2021YFB2206600) （2021YFB2206600）
