CAN总线错误检测系统设计与分析OACSTPCD

To detect the error occurring during data transmission on the CAN bus as early as possible and fix the failure node promptly,a CAN bus error detection system with FPGA as the core controller is studied and designed.The system uses Verilog HDL to design the CAN controller to realize the parsing function of the CAN bus protocol.Analyzing the types of errors that occur on the bus can detect bit errors,padding errors,validation errors,format errors,and answer errors.The detection results are encapsulated in the UDP data seg-ment in a fixed format and sent to an upper computer for display through the UDP driver.The experiment in simulated CAN communi-cation environment shows that the system can accurately detect the errors on the CAN bus,indicating its potential application value in guaranteeing the stability of the bus communication.