集成电路与嵌入式系统2024，Vol.24Issue(8)：23-28,6.DOI:10.20193/j.ices2097-4191.2024.0011
CAN总线错误检测系统设计与分析
Design and analysis of CAN bus error detection system
马跃权 1葛化敏 1朱方野1
作者信息
- 1. 南京信息工程大学自动化学院,南京 210044
- 折叠
摘要
Abstract
To detect the error occurring during data transmission on the CAN bus as early as possible and fix the failure node promptly,a CAN bus error detection system with FPGA as the core controller is studied and designed.The system uses Verilog HDL to design the CAN controller to realize the parsing function of the CAN bus protocol.Analyzing the types of errors that occur on the bus can detect bit errors,padding errors,validation errors,format errors,and answer errors.The detection results are encapsulated in the UDP data seg-ment in a fixed format and sent to an upper computer for display through the UDP driver.The experiment in simulated CAN communi-cation environment shows that the system can accurately detect the errors on the CAN bus,indicating its potential application value in guaranteeing the stability of the bus communication.关键词
FPGA/CAN总线错误检测/CAN控制器/Verilog HDL/以太网UDPKey words
FPGA/CAN bus error detection/CAN controller/Verilog HDL/Ethernet UDP分类
信息技术与安全科学引用本文复制引用
马跃权,葛化敏,朱方野..CAN总线错误检测系统设计与分析[J].集成电路与嵌入式系统,2024,24(8):23-28,6.
