电子与封装2024，Vol.24Issue(8)：69-75,7.DOI:10.16257/j.cnki.1681-1070.2024.0118
基于FPGA的基带信号发生器IP核设计与验证
Design and Verification of IP Core of Baseband Signal Generator Based on FPGA
闫华 1何志豪1
作者信息
- 1. 无锡中微亿芯有限公司,江苏无锡 214072
- 折叠
摘要
Abstract
The signal transceiver module in the radar system needs to generate baseband signals internally.To meet this requirement,the baseband signal generator IP core is designed based on direct digital frequency synthesis(DDS)technology,enabling customization of starting slope and starting frequency.The output frequency of the IP core is designed according to the characteristics of linear frequency modulation signals.Combining phase truncation method with CORDIC algorithm,the sine-cosine lookup table of the DDS module is designed to reduce resource occupancy and power consumption and enhance operational speed.Simulation results demonstrate that the designed IP core can normally output sine and cosine waveforms at different frequencies as well as linear frequency modulation signal waveforms,and can realize customizable adjustments,and show high flexibility.Compared to generating mixed-frequency waveforms through multiple DDS superposition,this IP core occupies fewer resources while maintaining practical value.关键词
FPGA/DDS技术/基带信号产生模块Key words
FPGA/DDS technology/baseband signal generation module分类
信息技术与安全科学引用本文复制引用
闫华,何志豪..基于FPGA的基带信号发生器IP核设计与验证[J].电子与封装,2024,24(8):69-75,7.
