电子与封装2024，Vol.24Issue(11)：14-21,8.DOI:10.16257/j.cnki.1681-1070.2024.0175
芯粒互连测试向量生成与测试方法研究
Research on Vector Generation and Testing Method for Chiplet Interconnection Testing
解维坤 1李羽晴 2殷誉嘉 2王厚军3
作者信息
- 1. 电子科技大学自动化工程学院,成都 611731||中国电子科技集团公司第五十八研究所,江苏无锡 214035
- 2. 中国电子科技集团公司第五十八研究所,江苏无锡 214035
- 3. 电子科技大学自动化工程学院,成都 611731
- 折叠
摘要
Abstract
Both 2.5D and 3D integrated system products based on Chiplet have a large number of Chiplet interconnections,which inevitably lead to various manufacturing defects.Interconnection testing is crucial to improving the quality and yield of 2.5D and 3D integrated system products during large-scale production.Based on the study of traditional interconnection testing methods such as I-ATPG and true/complement testing algorithm,a new code word encoding method is proposed,which only requires 4 code words to encode all rectangular and hexagonal networks.A test architecture of Chiplet integrated system based on IEEE 1838 standard is designed,and a typical dual-Chiplet interconnection circuit is presented and tested and verified by simulation,so as to systematically introduce Chiplet interconnection testing technology.关键词
芯粒/互连测试/可测性设计Key words
Chiplet/interconnection testing/design for testability分类
信息技术与安全科学引用本文复制引用
解维坤,李羽晴,殷誉嘉,王厚军..芯粒互连测试向量生成与测试方法研究[J].电子与封装,2024,24(11):14-21,8.
