电子与封装2024，Vol.24Issue(12)：64-70,7.DOI:10.16257/j.cnki.1681-1070.2024.0172
面向大规格矩阵协方差运算的高性能硬件加速器设计
Design of High Performance Hardware Accelerator for Large-Scale Matrix Covariance Computation
摘要
Abstract
With the development of radar systems toward multi-channel and high bandwidth,the real-time problem of covariance operation caused by large-scale matrix limits the application of space-time adaptive processing(STAP)technology in advanced airborne radar platforms.A high performance hardware accelerator design method is proposed to meet the increasing demand for large-scale matrix covariance processing and improve computational efficiency under low-power constraints.The accelerator is composed of computing unit,control module,storage module and DMA controller.It can support up to 256x8 192 matrix covariance operation under the condition of limited hardware storage resources by processing the matrix in column segments.The control logic of the lower triangulation operation is designed to reduce the amount of computation,and a high-concurrency ping-pong storage mechanism along with a pipelined multiplication-accumulation tree processing method are proposed to enhance the processing efficiency.The tape-out test results show that the performance of the hardware accelerator in large-scale matrix covariance operations is more than 70 times that of a CPU core with similar computational capabilities.关键词
协方差/硬件加速器/流水计算/乘累加树/乒乓存储Key words
covariance/hardware accelerator/pipeline computation/multiplication-accumulation tree/ping-pong storage分类
信息技术与安全科学引用本文复制引用
陈铠,刘传柱,冯建哲,滕紫珩,李世平,傅玉祥,李丽,何国强..面向大规格矩阵协方差运算的高性能硬件加速器设计[J].电子与封装,2024,24(12):64-70,7.基金项目
国家自然科学基金企业创新发展联合基金重点项目(U21B2032) （U21B2032）
