电子与封装2025，Vol.25Issue(6)：93-99,7.DOI:10.16257/j.cnki.1681-1070.2025.0060
一种支持循环缓冲的中断系统的设计与验证
Design and Verification of an Interrupt System Supporting Loop Buffering
摘要
Abstract
An efficient and secure interrupt processing system is designed for high-performance digital signal processor(DSP)based on very long instruction word(VLIW)structure,which supports 12 levels of maskable interrupts,non-maskable interrupts(NMIs),and hardware and software interrupt nesting.To address the disruption of program flow caused by loop buffer interrupts,a special interrupt response and processing mechanism is designed to ensure that in the case of high-frequency interrupts,the data processing in the loop buffer is not affected by interrupts,thus avoiding data loss or program crashes.The interrupt processing flow is optimized based on the characteristics of the VLIW structure,and the interrupt response delay is reduced.Simulation results show that the interrupt response time of this design is 25％shorter than that of the traditional method,and it ensures the data integrity and execution security of complex programs during interrupt processing.关键词
中断响应/中断处理/中断嵌套/中断返回/循环缓冲中断Key words
interrupt response/interrupt processing/interrupt nesting/interrupt return/loop buffer interrupt分类
信息技术与安全科学引用本文复制引用
沈一帆,谭勋琼..一种支持循环缓冲的中断系统的设计与验证[J].电子与封装,2025,25(6):93-99,7.基金项目
湖南省制造业关键产品"揭榜挂帅"项目(2022GXGG012) （2022GXGG012）
