电子与封装2025，Vol.25Issue(10)：49-54,6.DOI:10.16257/j.cnki.1681-1070.2025.0108
基于JESD204B协议的信号采集电路系统设计
Design of Signal Acquisition Circuit System Based on JESD204B Protocol
陈光威 1陈呈 1陈文涛 1王超 1张志福1
作者信息
- 1. 中国电子科技集团公司第五十八研究所,江苏无锡 214035
- 折叠
摘要
Abstract
A high-speed signal acquisition circuit system based on JESD204B protocol has been designed and implemented.The system adopts a four-channel JESD204B synchronous structure,an FPGA,a high-speed analog-to-digital converter(ADC),a gigabit user datagram protocol(UDP)network port,and double data rate fourth generation(DDR4)synchronous dynamic random access memory(SDRAM).The FPGA is interconnected with the ADC through JESD204B high-speed serial protocol interface for four-channel synchronous high-speed analog-to-digital conversion data acquisition,with a signal sampling rate of 3.2 GHz,achieving intermediate frequency signal sampling with a bandwidth of 1 GHz between 1.9 GHz and 2.9 GHz.The system focuses on the hardware design considerations for high-speed AD circuits,the structural design for matching JESD204B channel synchronization,upper computer-controlled data acquisition,4-channel ADC data caching,network port data flow control and transmission,and other key designs.By analyzing the indicators of the data received by the upper computer,the reliability and stability of the system operation are verified.关键词
JESD204B同步结构/FPGA/4通道同步高速ADC/DDR4流控Key words
JESD204B synchronous structure/FPGA/four-channel synchronous high-speed ADC/DDR4 flow control分类
电子信息工程引用本文复制引用
陈光威,陈呈,陈文涛,王超,张志福..基于JESD204B协议的信号采集电路系统设计[J].电子与封装,2025,25(10):49-54,6.
