电子与封装2025，Vol.25Issue(10)：55-61,7.DOI:10.16257/j.cnki.1681-1070.2025.0117
一款用于高性能FPGA的多通道HBM2-PHY电路设计
Design of Multi-Channel HBM2-PHY Circuit for High Performance FPGA
徐玉婷 1孙玉龙 1曹正州 1张艳飞 1谢达2
作者信息
- 1. 中微亿芯有限公司,江苏无锡 214072
- 2. 中微亿芯有限公司,江苏无锡 214072||智能汽车安全技术全国重点实验室,重庆 401133
- 折叠
摘要
Abstract
A multi-channel HBM2-PHY circuit is designed for high-speed and reliable data transmission between high-performance field programmable gate array(FPGA)and dynamic random access memory(DRAM).The circuit is designed using a 12 nm process to support up to eight independent channels and a data transfer rate of up to 1.6 Gbit/s.The FIFO cache is designed in the address and data paths of HBM2-PHY circuit to improve the data read and write efficiency.By designing adjustable delay chain circuit,the data sampling clock in high-speed receiving and transmitting circuits is adjusted,and the reliability of data transmission is improved.The simulation results show that the delay of the sampled clock signal can be adjusted by 512 steps,the delay time of each step is 0.003 ns,and the integral nonlinearity(INL)is 0.3 LSB.The eye view shows that the high-speed receiving and transmitting circuits perform well at a data rate of 1.6 Gbit/s.关键词
FPGA/高带宽存储器/DRAM/高级可扩展接口/双倍数据速率Key words
FPGA/high bandwidth memory/DRAM/advanced extensible interface/double data rate分类
电子信息工程引用本文复制引用
徐玉婷,孙玉龙,曹正州,张艳飞,谢达..一款用于高性能FPGA的多通道HBM2-PHY电路设计[J].电子与封装,2025,25(10):55-61,7.
