电子与封装2025，Vol.25Issue(11)：41-49,9.DOI:10.16257/j.cnki.1681-1070.2025.0164
一种用于FPGA测量时钟延迟的方法
Method for Measuring Clock Delay in FPGA
闫华 1匡晨光 2陈波寅 2刘彤 2崔会龙2
作者信息
- 1. 无锡中微亿芯有限公司,江苏无锡 214072||智能汽车安全技术全国重点实验室,重庆 401133
- 2. 无锡中微亿芯有限公司,江苏无锡 214072
- 折叠
摘要
Abstract
As a key part of the field programmable gate array(FPGA)circuit,the clock currently has problems such as large errors and difficulties in building test cases in the test methods.Based on the existing FPGA architecture,a new test method that converts the clock delay of the part to be tested into the duty cycle of the output clock is proposed.The research results show that the new test method successfully shields the error interference brought by external test devices,reduces the difficulty of building test cases,and greatly expands the test range of the clock delay in the chip.And it provides a strong guarantee for building an accurate timing library for FPGA.关键词
FPGA时序库/FPGA架构/时钟测试Key words
FPGA timing library/FPGA architecture/clock test分类
信息技术与安全科学引用本文复制引用
闫华,匡晨光,陈波寅,刘彤,崔会龙..一种用于FPGA测量时钟延迟的方法[J].电子与封装,2025,25(11):41-49,9.
