电子与封装2025，Vol.25Issue(11)：50-54,5.DOI:10.16257/j.cnki.1681-1070.2025.0130
一种40 GSample/s超高速采样保持电路
40 GSample/s Ultra-High-Speed Sample-and-Hold Circuit
摘要
Abstract
An ultra-high-speed broadband sample-and-hold circuit was designed based on a 0.7 μm indium phosphide(InP)heterojunction bipolar transistor(HBT)process.The nonlinearity of the input buffer is effectively reduced through an emitter resistor degradation structure.The switch core circuit employs cross-coupling to reduce feedthrough in hold mode.Post-simulation results show that the designed circuit operates stably at a sampling rate of 40 GSample/s.At the Nyquist input signal frequency,the circuit achieves a spur-free dynamic range(SFDR)exceeding 40 dBc.When a 12.1 GHz,-4 dBm signal is input,the circuit achieves an SFDR of 51 dBc,with an effective number of bits of approximately 8 bit.关键词
采样保持电路/超高速/宽带/磷化铟/异质结双极型晶体管Key words
sample-and-hold circuit/ultra-high-speed/broadband/indium phosphide/heterojunction bipolar transistor分类
信息技术与安全科学引用本文复制引用
赵安,李浩,张有涛,罗宁,张长春,张翼..一种40 GSample/s超高速采样保持电路[J].电子与封装,2025,25(11):50-54,5.基金项目
国家自然科学基金(61804081) （61804081）
微波毫米波单片集成和模块电路重点实验室基金重点项目(614280304012101) （614280304012101）
南京邮电大学科学研究基金(NY221065) （NY221065）
国家留学基金(CSC202108320189) （CSC202108320189）
