电子与封装2026，Vol.26Issue(1)：57-61,5.DOI:10.16257/j.cnki.1681-1070.2026.0008
基于锁相环的Flash FPGA时钟网络架构设计
Design of a Phase-Locked Loop-Based Flash FPGA Clock Network Architecture
王雪萍 1蔡永涛 1张长胜 1马金龙1
作者信息
- 1. 中国电子科技集团公司第五十八研究所,江苏无锡 214035
- 折叠
摘要
Abstract
A Flash FPGA clock network architecture based on phase-locked loop(PLL)is designed.The number of global clocks is expanded to three,and two additional core-output clocks are added in this architecture.One PLL-equipped clock conditioning circuit and five non-PLL clock conditioning circuits are implemented around the chip periphery to achieve frequency division,frequency multiplication,phase shift,and delay functions.Simulation results demonstrate that this architecture can meet the timing configuration requirements of the entire chip.Actual tape-out tests indicate that the maximum operating frequency of the architecture reaches 350 MHz,a significant improvement over the original clock conditioning circuit(180 MHz)and comparable to that of similar-scale international products.关键词
Flash FPGA/锁相环/时钟网络Key words
Flash FPGA/phase-locked loop/clock network分类
信息技术与安全科学引用本文复制引用
王雪萍,蔡永涛,张长胜,马金龙..基于锁相环的Flash FPGA时钟网络架构设计[J].电子与封装,2026,26(1):57-61,5.
