电子元件与材料2026，Vol.45Issue(1)：27-34,8.DOI:10.14106/j.cnki.1001-2028.2026.1295
一种高电源抑制比低功耗LDO设计
A LDO design with high power supply suppression ratio and low static current
师全涛 1吴巍 2王俊峰1
作者信息
- 1. 南京邮电大学 集成电路科学与工程学院,江苏 南京 210023||南京宇都通讯科技有限公司,江苏 南京 210046
- 2. 南京宇都通讯科技有限公司,江苏 南京 210046
- 折叠
摘要
Abstract
In order to meet the requirements of radio frequency(RF)circuits for high power supply rejection(PSR)and low power consumption in the mid-to-high frequency range,this paper proposed a low-dropout regulator(LDO)design featuring both high power supply rejection ratio and low power consumption.By introducing a low-output-impedance buffer and an adaptive dynamic zero compensation circuit between the output of the error amplifier and the gate of the power transistor,the system stability was ensured while extending the PSR bandwidth,thus achieving high power supply rejection characteristics in the mid-to-high frequency range.The adoption of a buffer that combines fixed bias and adaptive bias,together with a sub-threshold CMOS reference with lower static current,effectively reduced the overall power consumption of the circuit.The proposed circuit was designed based on the SMIC 55 nm CMOS process,supporting an overall supply voltage range of 1.7-3 V,an output voltage of 1.2 V,and a load current range of 500 μA-50 mA.Experimental results indicate that when the load current is 50 mA,the LDO achieves a PSR of-61.2 dB at 100 kHz and-63 dB at 1 MHz,with a minimum quiescent current of only 40.4 μA.This LDO is therefore suitable for electronic devices sensitive to power supply ripple.关键词
电源抑制比/稳定性/零点补偿/低静态电流/自适应偏置/CMOS基准Key words
power suppression ratio/stability/zero-point compensation/low static current/adaptive bias/CMOS reference分类
信息技术与安全科学引用本文复制引用
师全涛,吴巍,王俊峰..一种高电源抑制比低功耗LDO设计[J].电子元件与材料,2026,45(1):27-34,8.
