电子元件与材料2026，Vol.45Issue(5)：558-565,8.DOI:10.14106/j.cnki.1001-2028.2026.1489
Σ-ΔADC动态可重构数字抽取滤波器面积优化
Area optimization of a Σ-ΔADC digital decimation filter with dynamic reconfiguration
摘要
Abstract
To meet the increasing demands for high precision and flexibility in communication,radar,and edge computing applications,this paper proposed a dynamically reconfigurable digital decimation filter based on a hybrid LUT-multiplier architecture.The design employed non-uniform coefficient quantization guided by frequency response sensitivity and noise analysis,combined with LUT compression technology to effectively reduce storage and computation overhead.A dynamic reconfiguration mechanism was introduced to realize real-time adjustment of filter coefficients and decimation factors(64,128,512),enabling switching between decimation factors to meet varying bandwidth and performance requirements.The filter consists of a five-stage cascaded integrator-comb(CIC)filter cascaded with a finite impulse response(FIR)compensator,exhibiting highly flexible performance reconfigurability.FPGA validation results showed that the filter could efficiently complete decimation and filtering tasks across multiple bandwidths.Implemented in a 0.18 μm CMOS process,the design underwent logic synthesis and layout design,occupying an area of 0.289 mm2,achieving a peak SNR of about 105 dB and an ENOB of 16.3 bit.Compared with conventional fixed-structure filter schemes,the chip area was reduced by approximately 20%.This dynamically reconfigurable design significantly enhances system adaptability and resource utilization efficiency,making it suitable for high-performance and multi-scenario application requirements.关键词
数字抽取滤波器/非均匀量化/芯片面积/FIR滤波器/动态重构Key words
digital decimation filter/nonuniform quantization/chip area/FIR filter/dynamic reconfiguration分类
信息技术与安全科学引用本文复制引用
闫宇,崔杰,苏杰,孙嘉晨,陈磊..Σ-ΔADC动态可重构数字抽取滤波器面积优化[J].电子元件与材料,2026,45(5):558-565,8.基金项目
国家自然科学基金(62001232) （62001232）
