电子与封装2026，Vol.26Issue(6)：21-25,5.DOI:10.16257/j.cnki.1681-1070.2026.0066
基于JTAG的非完全BS结构的SiP芯片内部互连测试
Internal Interconnection Testing of SiP Chips with Incomplete BS Structures Based on JTAG
华枫 1张秀均 1辛赟龙1
作者信息
- 1. 无锡中微亿芯有限公司,江苏无锡 214072
- 折叠
摘要
Abstract
Boundary scan(BS)technology based on the joint test action group(JTAG)protocol enables interconnect testing.However,there is limited research on interconnect testing for bare dies in system-in-package(SiP)chips with incomplete BS scan structures.To address this issue,a testing method utilizing serial vector format(SVF)and boundary scan description language(BSDL)files is proposed.This method controls Flash devices without BS structures via a field-programmable gate array(FPGA)containing BS ports,verifying whether interconnects between bare dies in SiP chips function properly.Practical waveform validation confirms the feasibility of this approach.关键词
SiP/边界扫描/SVF/BSDL/互连测试Key words
SiP/boundary scan/SVF/BSDL/interconnect testing分类
信息技术与安全科学引用本文复制引用
华枫,张秀均,辛赟龙..基于JTAG的非完全BS结构的SiP芯片内部互连测试[J].电子与封装,2026,26(6):21-25,5.
