Low-complexity systolic architecture for inversionOA
Low-complexity systolic architecture for inversion
A modified extended binary Euclid's algorithm which is more regularly iterative for computing an inversion in GF(2m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has are…查看全部>>
A modified extended binary Euclid's algorithm which is more regularly iterative for computing an inversion in GF(2m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O(m), latency of 5m-2, and throughput of 1/m. Compared with other serial systolic architectures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for …查看全部>>
Yuan Danshou;Rong Mengtian
Department of Electronics Engineering, Shanghai Jiaotong University, Shanghai 200030, P.R.ChinaDepartment of Electronics Engineering, Shanghai Jiaotong University, Shanghai 200030, P.R.China
建筑与水利
VLSIinversionsystolic arrayFinite field
VLSIinversionsystolic arrayFinite field
《高技术通讯（英文版）》 2006 (4)
413-416,4
Supported by the High Technology Research and Development Programme of China (No. 2003AA141040).
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