集成电路与嵌入式系统2024，Vol.24Issue(5)：55-59,5.
电磁脉冲应力下MOSFET器件退化机制研究
Study on degradation mechanism of MOSFET devices under electromagnetic pulse stress
摘要
Abstract
In response to issues such as abnormal degradation of chip performance caused by electromagnetic pulses in power application scenarios,and unclear failure mechanisms of devices such as MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistors)within the chip,TLP(Transmission Line Pulse)pulses,with amplitude and width of 8 V and 100 ns,are applied into gate oxide layer of 5 V NMOS devices.The output characteristic curves Id-Vd and the transfer characteristic curves Id-Vg under different pulse cycles are measured.By calculating the device transconductance under different TLP number,the threshold voltage VT and carrier mobility with TLP pulse are obtained.The test results show that under the same drain voltage Vd and gate voltage Vg,the drain current Id of the device increases with the increase of the number of TLP pulses.TLP pulses cause a significant decrease of VT,which decreases by about 25.66％under 20 000 TLP pulses,TLP pulses caused the VT of the device to increase exponentially,and the fitting index is between 0.11～0.15.The influence of TLP pulses on the carrier mobility in the channel is not obvious.关键词
金属氧化物半导体场效应管/电磁脉冲/阈值电压/跨导/迁移率Key words
MOSFET/electromagnetic pulse/threshold voltage/transconductance/mobility分类
信息技术与安全科学引用本文复制引用
宋斌斌,王凯,鹿祥宾,单书珊,罗宗兰,栗磊,赫嘉楠..电磁脉冲应力下MOSFET器件退化机制研究[J].集成电路与嵌入式系统,2024,24(5):55-59,5.基金项目
国家电网有限公司总部科技项目资助(基于失效风险评估的继电保护防存储单元异常以及加固技术研究:5100-202335010A-1-1-ZN). （基于失效风险评估的继电保护防存储单元异常以及加固技术研究:5100-202335010A-1-1-ZN）
